asynchronous clock
英 [eɪˈsɪŋkrənəs klɒk]
美 [eɪˈsɪŋkrənəs klɑːk]
网络 异步时钟
双语例句
- Fault Detection for Networked Control Systems with Long Time-delay of Asynchronous Clock
具有长时延和异步时钟的网络控制系统的故障检测 - Application of asynchronous circuits has become one of the most promising directions in circuit design because asynchronous circuits are free of clock skews.
异步电路因不受时钟偏差的限制而逐渐成为电路设计研究的热点。 - Asynchronous interrupts are generated by other hardware devices at arbitrary times with respect to the CPU clock signals.
异步中断是由其他硬件设备产生的，可以在CPU时钟信号的任意时刻到来。 - Asynchronous Clock Designs; Clifford E.Cummings.
非常精典的异步时钟域设计文章。 - According to different sensitive transitions of flip-flops used in sequential circuits, design and analysis methods for asynchronous sequential circuits are proposed by using the combinatorial clock.
本文根据电路中采用的触发器的不同敏感沿，提出采用组合时钟的异步时序电路的设计和分析方法。 - Asynchronous FIFO is a general way to communicate between different clock domains.
异步FIFO是一种不同时钟域之间传递数据的常用方法。 - A Standard Method to Find internal Clock Pulse Overlay Area by Karnaugh Map ── Analysis of Asynchronous Sequential Logic Circuit in the Case or Comples Clock Pulse
利用卡诺图寻找内时钟复盖区的规范方法&复杂时钟下异步时序罗辑电路分析 - This paper presents a new method to design asynchronous sequential circuit: clock signals and secondary state Karnaugy Map uniting method.
提出了一种异步时序电路设计的新方法：时钟信号与次态卡诺图联立法。 - Asynchronous design methodology has become one of the most promising directions in SOC design because asynchronous circuit possesses the advantages of low power, low noise, no clock skew, high robust and modularization.
异步电路在低功耗、低噪声、抗干扰、无时钟偏移和模块化设计等方面有较高的性能。在SOC芯片设计中，异步设计技术逐渐成为研究的热点。 - The Study of Synchronizer Design in Asynchronous Clock Domain System
异步多时钟域系统的同步设计研究 - The problem with transmitting bus signals between asynchronous clock domains.
总线信号跨时钟域传输的问题首先介绍了高级数据路径设计的思想。 - In order to improve the quality of image acquired, the causes of high-speed tri-CCD color disorder were analyzed, and several approaches including prismatic decomposition, exposure controlled by asynchronous trigger clock, and correction by software, are suggested for correction of high-speed tri-CCD color disorder.
为了改善图像采集的质量，通过分析高速彩色线阵CCD三色错位产生的机理，提出了三色错位的几种修正方法：棱镜分光法、异步时钟控制曝光法、通过软件修正法。 - An asynchronous clock can be used to control the exposures so that the sequence and delay of tri-CCD exposures can be adjusted to avoid color disorder.
改变现有CCD外围电路，通过异步时钟控制曝光，即调整CCD曝光的先后次序和延迟时间，实现错位修正； - Design of Asynchronous Sequential Logic Circuit Based on Design of Clock Signal
基于时钟设计的异步时序逻辑电路设计法 - The master clock can be asynchronous with PCM data side clock or ADPCM data side clock. Using an 8-depth async FIFO solves the synchronization and exchange of data be-tween different clock domains.
主时钟与PCM数据端时钟或ADPCM数据端时钟可以是异步的，不同的时钟控制范围内的数据同步或交换是通过一个深度为8的FIFO来实现的； - The Synchronization in the Asynchronous Clock Design for FPGA
FPGA异步时钟设计中的同步策略 - Because the short time interval which is asynchronous between the time interval measured and the clock pluses filled exists in the any time measurement.
因为对任意的时间测量都存在着被测时间间隔与填充脉冲之间所不同步的短时间间隔。 - On designing a asynchronous counter, not only the uneffective item, but also that the clock pulse unused should be treated as the laced item.
在异步计数器设计中，除了无效的状态外，凡是时针脉冲不起作用的时刻，电路的状态也应当成约束项来处理。 - On the basis of the analysis to the framework of liquid crystal display ( LCD) controllers, a method to settle concurrent access of the display storage and asynchronous clock by asynchronous FIFO ( first in first out) circuit was studied.
在分析液晶显示（LCD）控制器总体结构的基础上，阐述了用异步FIFO（先进先出）电路来解决显示存储器的并发访问和异步时钟域问题。 - Design and Analysis of Asynchronous Sequential Circuits by Using Combinatorial Clock
采用组合时钟的异步时序电路分析和设计 - The application of network router shows that the asynchronous FIFO interface based of Gray code can solve the problem of clock domain switching pithily and efficiently.
经过在网络路由器的应用表明，基于Gray码的异步FIFO接口能够简洁、高效的解决时钟域切换的问题。 - Design of Synchronization Technology for Asynchronous Multi-clock System
异步多时钟系统的同步设计技术 - Network on chip is a new multi-cores interconnect technology, which separates data processing elements and communication resources and has good parallel communication skill and scalability. It uses global asynchronous locally synchronous technology in order to solve a single clock problem of system on chip.
片上网络是一种新的多核互连技术，它将数据处理与通信资源独立开来，具有良好的并行通信能力和扩展性，采用全局异步局部同步技术彻底解决了片上系统的单一时钟问题。 - The power differential protection scheme provides a way that is not affected by asynchronous clock, and it makes up for a deficiency, that is the current differential protection must be locked when the clock is asynchronous.
功率差动保护提供了一种不受异步影响的方案，弥补了电流差动在同步信号故障时必须退出运行的不足。 - According to the refresh characteristic of Dynamic Random Access Memory, the design uses asynchronous FIFO to achieve the data transfer through ADC, DDR2 memory chips and DSP clock domain.
同时根据动态存储器的刷新特性，设计了异步FIFO，实现了A/D采样、DDR2内存芯片和DSP三者之间的数据传递。 - During the discussion of key issues, on the core issues of the modular design, including issues dealing with asynchronous clock domains, the source synchronous technology and high-speed signal integrity issue of electronic system in-depth analysis and discussion.
在关键问题讨论中，对模块设计中的核心问题，主要包括异步时钟域问题的处理、源同步技术的应用和高速电子系统中的信号完整性问题进行了深入的分析与探讨。 - GALS ( Globally asynchronous, locally synchronous) architecture is a promising solution for NoC clock distributing, it could effectively reduce the clock tree power consumption.
GALS（全局异步、局部同步）架构适用于NoC的时钟分布，它能有效地减少时钟树上的功耗消耗。 - FIFO module is used for solving the issue of asynchronous clock read and write cache; CRC module checkouts both data of sender and receiver; the serial-parallel converter module is used for the data conversion between the 8 parallel data and serial data.
其中FIFO模块用于解决异步时钟读写缓存问题；CRC模块用于收发双方校验数据；串并转换模块用于实现8路并行数据和串行数据的转换。 - Among them, the structure employs asynchronous FIFO to transfer data between different clock domains, effectively avoiding the appearance of metastable state.
其中，采用异步FIFO结构解决了不同时钟域之间的数据交换，有效地避免亚稳态的出现。